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Altera_Forum
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13 years ago

Problems with simulation of DDR2 SDRAM Controller with UniPHY

Hi, I Am using the files for simulation in generated for this IP . The IP is configured to enable Hard external memory controller, in Aria V, Quartus 12. The DDR2 SDRAM Controller is set...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I have also noticed the problems with afi_half_clk when upgrading to Quartus 12.1 When digging into the generated code for the pll the second to last line is "assign afi_half_clk = 1'b0;" I am pretty sure that is the source of the problem there. For the time being i an creating an external Pll to divide down the clock.

-Brian