Honored Contributor
Honored ContributorThe config you show there has 1 channel with an input sample rate that's 3/4 of the clock rate. To function correctly FIR Compiler II would expect data to appear at the input with the following valid pattern:
Valid: 1, 1, 1, 0, 1, 1, 1, 0, ... While it can cope with extra pauses, it cannot cope with data being provided too quickly. (You might think the Back Pressure Support checkbox would solve this but in reality this only passes through back pressure signals from an upstream sink. Hopefully this will be resolved in a future release). The reason it works when your sample rate is higher than your clock rate, is that then the valid signal is expected to be high on every cycle so it doesn't get confused.
