problems creating qsys component, understanding Avalon master& slave reads

Hi, I managed to get the code compiled without errors for my component BUT now the problem ist it won't fit into the device and I find that a bit strange, maybe somebody can shed some light on it, please.

The error message Quartus is giving is : Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis

I tried finding out what part of the code could cause this and when I just comment out the

if (currentBockToReplace = '0') then
  cacheBlocksMemory(currentBlock0MemoryOffset + 15) <= tempBuffer0 & tempBuffer1;
  cacheTags(currentBlock0DescriptorIndex) <= currentTag;
  cacheUsed(currentBlock0DescriptorIndex) <= '1';
  cacheValids(currentBlock0DescriptorIndex) <= '1';
  cacheUsed(currentBlock1DescriptorIndex) <= '0';
else
  cacheBlocksMemory(currentBlock1MemoryOffset + 15) <= tempBuffer0 & tempBuffer1;
  cacheTags(currentBlock1DescriptorIndex) <= currentTag;
  cacheUsed(currentBlock1DescriptorIndex) <= '1';
  cacheValids(currentBlock1DescriptorIndex) <= '1';
  cacheUsed(currentBlock0DescriptorIndex) <= '0';
end if;

part of the buffering case in read_fsm the error is gone and it compiles just fine.

I can not wrap my head around why this is happening, can someone have a look please?

THX

Grobi