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Altera_Forum
Honored Contributor
14 years agoHi,
I made a port map change in the code that is obtained from the mega core...... I mapped the rx_coreclk & the tx_coreclk to the tx_clkout of the system now the error is removed and i generated the programming file,,,,,,,,,,in the quartus design flow.......... Is this is correct ...........what i did..............