Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorproblem with PCIe troughput in CIV GX DevKit
hi friends i have a problem with the PCIe in the cyclone IV FPGA: i have implement the PCIe HIP using Qsys on Quartus II 11.0 with the modular SGDMA and a On-Chip-Memory. i connect the CIV...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Can you please look at the number of lanes the link negotiated to? Hello, Dave! While testing the Qsys PCIe core in x4 mode, I found that the core negotiated to either x1, x2, or x4. --- Quote End --- Dit it happen on the same PC - one time the core negotiated to x1 and another time to x4? I have an issue, that PCIe core in a custom board on one PC always negotiates to x4 and on the other - always to x1. What could be the cause?
