Honored Contributor
Honored ContributorHi Josef,
--- Quote Start --- I am currently also having this issue! Have either of you been able to find the answer to this? --- Quote End --- No, I went with a different PCIe solution (using an MPC8308 PowerPC). --- Quote Start --- As for an actual solution, this is the closest I've found so far: http://www.altera.com/support/kdb/solutions/rd03092011_589.html Apparently you have to write to the Link Control register located at 0x90, but how? --- Quote End --- Re-read the KB link again: "software must set bit 5 of Link Control register in the root port to trigger retraining link" If your board is PCIe device, the root-complex is the host PC. To trigger retraining there, you would have to trigger something using OS services, eg., under Linux use PCI hotswap to trigger re-enumeration. I've no idea how you would do something similar with Windows. File a Service Request with Altera and see what they say. Perhaps there is something you can do with the core, or perhaps you can trace the negotiation phases and see why it decides to reduce the lane width, eg., did the host decide or the peripheral? Cheers, Dave
