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i have a problem with the PCIe in the cyclone IV FPGA:
i have implement the PCIe HIP using Qsys on Quartus II 11.0 with the modular SGDMA and a On-Chip-Memory.
i connect the CIV with my PC using windriver Application. i use some functions to mesure the throughput.
the problem is that i have the same throughput even if i use x1 or x4 implemention ( 208 MBytes/s), and normaly in x4 configuration that can be four times this result.
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Can you please look at the number of lanes the link negotiated to?
While testing the Qsys PCIe core in x4 mode, I found that the core negotiated to either x1, x2, or x4. I have not yet determined why. I'd be interested in hearing if you are facing the same issue.
Here's a thread with my test results. Look at the document. It has comments on using lspci to determine the link width.
http://www.alteraforum.com/forum/showthread.php?t=35678 Cheers,
Dave
Honored Contributor
