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Altera_Forum
Honored Contributor
Honored ContributorProblem with integer variable and vector range
My code: Int is an Integer Variable OutputNumber is a Std_logic_Vector Input Int <= conv_integer(OutputNumber); MyVector(37 downto (38-Int)) <= Temp(37 downto (38-Int)); Quart...
Altera_ForumHonored Contributor
Honored ContributorAmilcar has already explained, that your code isn't valid VHDL. Try as I suggested or use a similar construct according to VHDL syntax rules.
