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Altera_Forum
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16 years ago

Problem with integer variable and vector range

My code: Int is an Integer Variable OutputNumber is a Std_logic_Vector Input Int <= conv_integer(OutputNumber); MyVector(37 downto (38-Int)) <= Temp(37 downto (38-Int)); Quart...
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Altera_Forum
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16 years ago

The VHDL standard does not allow the right-hand side of downto expresions to contain a variable.

Just use a constant instead of a Int Integer variable.