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xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Problem with CXL IP Design Example Type 3 on DK-DEV-AGI027RBES

Hi,

We are using Quartus 24.1 to compile the type 3 ddr memory design example for the board and program the FPGA using the following guide:

Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA IP Design Example User Guide version 1.12 for quartus 24.1.

If we program it with the recommended SW4 switch setting (4.1 ON), it does not work and we loose access to the FPGA with a JTAG chain broken error (same as this https://community.intel.com/t5/Programmable-Devices/JTAG-error-after-programming-device/td-p/1594877)

The same happens if we leave SW4 to the preset configuration (4.3 ON).

If we program the device with all SW4 pins to OFF (as it was for the R1BES version of the board) we can still detect the FPGA but programming fails with the attached configuration errors. The description states: "External hardware access error. The first i2c command has failed, no response from voltage regulator".



Could you please let me know what is the correct SW4 setting and how we should proceed?

Best Regards,
Alverti Chloe

Best Regards,

Chloe

Cxl
  • xalverti's avatar
    xalverti
    2 years ago

    Hi again,

    The problem was on the PCIe slot on the server side.

    We replaced our card and the problem was fixed.

    For anyone facing the same problems, we had to check the x16 slot with other devices to identify the lane drop issue in BIOS.

    CXL IP designs apparently are note recognized in BIOS as PCIe devices even when the design is working -- the corresponding PCIe slot always shows the message "Link did not train" -- as if nothing is attached on the slot.

    Thank you for your help,

    Chloe

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  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi there,

    Do we have some progress on this issue?

    Best regards,

    WZ


  • xalverti's avatar
    xalverti
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,

    Thank you for your reply -- We are trying to figure out if it is a server problem as you pointed out.

    Our server is CXL compatible but we may face a PCIe drop lane issue.

    As a clarification the CXL IP cannot tolerate 8 lanes on the PCIe slot, right?

    I will keep you posted once we have figured out.

    Best,

    Chloe

    • xalverti's avatar
      xalverti
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi again,

      The problem was on the PCIe slot on the server side.

      We replaced our card and the problem was fixed.

      For anyone facing the same problems, we had to check the x16 slot with other devices to identify the lane drop issue in BIOS.

      CXL IP designs apparently are note recognized in BIOS as PCIe devices even when the design is working -- the corresponding PCIe slot always shows the message "Link did not train" -- as if nothing is attached on the slot.

      Thank you for your help,

      Chloe

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi there,

    So glad to hear that the issue has be solved. For your dilemma about training failed with *16, to be honest, we never meet the same issue. If we have chance, we will test it based on your description. Thanks for your effort.

    Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.

    Thank you for your time and cooperation.

    Best regards,
    WZ