CXL ARB/MUX initialization debug
Hi, I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server) (I am not sure I am writing to the appropriate board. If I need to move this post, please let me know ) Actually, I am not using the Intel CXL IP and implementing myself based on PCIE IP. and I am on the road to implement the FPGA that want to be connected to CPU as CXL.io & CXL.cache enabled(CXL type 1 device). But the problem is I am stuck at ARB/MUX layer initialization flow. (I already successfully done connecting CPU and FPGA as CXL.io only enabled . As CXL.io only enabled, ARB/MUX layer is set to bypassed so that ARB/MUX layer initialization flow is not required at this situation. ) In this above picture(Fig. 5-12) from the CXL specification, CPU(Left side) and Endpoint device(Right side) exchange the ALMPs(ARB/MUX link management packets) and finishes the state transition to active state. but the problem is that CPU is not responding the State_Status_Active_ALMP that notifies the CPU's ARB/MUX layer initialization is done even if previous ALMPs sent well from the endpoint device and received well to CPU. Can anybody help me with these problems ? Any similar circumstances or advices would be welcome Best,
CXL Type 3 + AXI Reg slice causing system deadlock
Hi all, I'm currently using the CXL Type 3 IP, and am encountering the following issue. Whenever I hook up the CXLIP directly to the MC, things work fine. However, when I place an AXI register slice between the CXLIP and the MC (which in theory should just add a one cycle latency), my system deadlocks when attempting a memory-intensive workload. I've used a couple of different AXI Reg slice implementations, including some online, some of my own, and some manual FIFO instantiations. I've narrowed it down to the AW, W, and AR channels (any manager-initiated ones); putting a FIFO on any of these paths causes deadlocks. I'm pulling my hair out, since I've confirmed that everything is compliant to AXI handshake specifications. Any ideas for next steps would be much appreciated.Inquiry about Device Compatibility and Version Support for AGIB027R29A1E2VR3 in Quartus Prime Pro V
During the New Project stage, the device model AGIB027R29A1E2VR3 is not available, but the Development Kit DK-DEV-AGI027R1BES is present. However, in the device model list, AGIB027R29A1E2VRC is found. Are VRC and VR3 the same device? Or is it that version 24.2 does not support the device AGIB027R29A1E2VR3? OS: Windows11 Quartus version:24.2
CXL IP Debug Toolkit
Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted by the Debug Toolkit seems to point to failures, but the documentation does not give details on the description of the registers. The most notable entries are: Local Retry State Machine,0x8c00 Num Local CRC Detected,0x2 Local FSM State Status,0x3 Viral Log,0x4 Link Received Viral,0x1 BBS Idle Status,0x0 BBS Error Status,0x1 BBS CXL Status Register Slice0,0xc0000000 BBS Error Status Register,0x12 Device Protocol Table Error,0x1 M2S Viral Received,0x1 BBS Error Status First Register,0x10 The counters show some interesting results. Even though a single Byte RwD was requested by the application, a Req also happened, and apparently only the Req was responded with DRS, whereas the RwD didn't trigger NDR to be sent: Counter of M2SReq Operations,0x1 M2SReq Counter,0x1 Counter of M2SRwD Operations,0x1 M2SRwD Counter,0x1 Counter of S2MDRS Operations,0x1 S2MDRS Counter,0x1 Counter of S2MNDR Operations,0x0 S2MNDR Counter,0x0 Is there more information available on the meaning of the registers for the CXL IP Debug Toolkit? Thank you, Ricardo PS: The complete dump of registers from the Debug Toolkit can be found attached.
sof file for CXL Type3 ED for DK-DEV-AGI027-RA?
Is there a pre-built CXL Type3 example design for DK-DEV-AGI027-RA with CXL IO on the PCIe fingers? I have built one myself, but I run into cyclic boots under Linux. I was wondering if there is a pre-built and verified sof for this design available to rule out problems with my own build. Right now I don't know if the problem is with my build or with BIOS settings required by the design. BTW I have a PCIe build working at Gen5 x16. I also have ASIC based CXL attached memory working on the same host.
Error in Xcelium simulation for CXL Type 3 example design
Hi, I am trying to simulate the CXL Type 3 example design using Xcelium simulator. I am getting error "error within protected source code". We are getting four types of Xcelium errors. xmvlog MIMPST xmvlog SVVMAP xmvlog DUPIDN xmvlog SVNOTY The error log is given below: file: /intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_soft_rx_tx_wrapper.sv xmvlog: *E,SVVMAP (/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_soft_rx_tx_wrapper.sv): error within protected source code. errors: 1, warnings: 0 file: /intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_soft_tx_wrapper.sv xmvlog: *E,SVVMAP (/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_soft_tx_wrapper.sv): error within protected source code. xmvlog: *E,SVVMAP (/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_soft_tx_wrapper.sv): error within protected source code. errors: 2, warnings: 0 file: /intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_reset_ctrl.sv xmvlog: *E,DUPIDN (/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/sim/soft_wrapper/rnr_cxl_reset_ctrl.sv): error within protected source code. errors: 1, warnings: 0 file: /intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_1130/sim/cxl_io_cmb_pf1_regs_2_rdl.sv xmvlog: *E,MIMPST (intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_1130/sim/cxl_io_cmb_pf1_struct_ports.vh.iv): error within protected source code. xmvlog: *E,SVNOTY (intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_1130/sim/cxl_io_cmb_pf1_struct_ports.vh.iv): error within protected source code. xmvlog: *E,MIMPST (intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_1130/sim/cxl_io_cmb_pf1_struct_ports.vh.iv): error within protected source code. xmvlog: *E,SVNOTY (intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_1130/sim/cxl_io_cmb_pf1_struct_ports.vh.iv): error within protected source code. . . libncprotect: *W,ENVDEPRREN: Environment Variable (NCPROTECT_KEYDB) is deprecated. Use (XMPROTECT_KEYDB) instead. errors: 208, warnings: 0IP license missing at generating programming file step, but these IPs are licensed
Hello support, I have been encountering a weird problem. We are working with CXL Type 3 example design. At the generate programming file step, Quartus complains about missing required license that is clearly listed on the license page. We couldn't resolve it through a number of ways: recompiling the design from scratch, using a different Quartus version, regenerating the CXL IP, and updating IPs. We really appreciate the help. Please refer below the quartus error message on the CXL IP (6AF7 0188), which shows up in the licensed IPs in license setup.Error: Quartus Prime Assembler was unsuccessful？CXL design example.
OS: Windows11 Quartus version:24.2 Device：AGIB027R29A1E1VB Development Kit: Agilex 7 FPGA I-Series Development Kit 2xR-Tile and 1xF-Tile DK-DEV-AGI027-RA Unable to generate CXL design example with Tile 14C or 15C： Error persists after checking and replacing the license. Error persists after changing the device type to AGIB027R29A1E2VR3 and Development Kit to R1BES. How should I solve this problem? Is it related to the Quartus Prime Pro software version?
