Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Problem with credits for PCIE IP

Hi,

I am working on a Stratix V PCIE Endpoint using the PCIE Hard IP and ran into a problem issuing packets. The block is configured to 128 byte payload, so that should be 8 data credits for a memory write (posted) request. The device starts off with a quite high credit limit and the value gets consumed as packets go through but it does not seem to be going back up. It goes down to having 5 credits at one point in time and then I stop sending write requests, waiting for the credits to be returned. The number seems to never rise again, and the device remains hanged waiting for the credits to rise again.

Anyone have any ideas? I thought that in this case the DLLPs were supposed to be raised in priority and the root then should be returning credits but I do not see any changes here.

I am using Quartus 14, it is a Avalon ST PCIE 256-bit.

Just looking quickly in lspci I get:

DevCap: MaxPayload 2048 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us

ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-

DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-

RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

MaxPayload 128 bytes, MaxReadReq 512 bytes

DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend+

LnkCap: Port# 1, Speed 8GT/s, Width x8, ASPM unknown, Latency L0<4us, L1 <1us

ClockPM- Surprise- LLActRep- BwNot-

LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+

ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported

DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled

LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-

Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The mistake was mine. I was confusing the tx_cred bus of the Stratix IV with the tx_cred_datafccp[11:0], fcnp, fcp busses on the Stratix V.

    The Stratix IV version gives the credits available, so if there are credits you can send a packet. Be careful that this is only for outgoing requests. You have to make sure you do not flood your RX buffer with the responses that come back from your outgoing MRd requests.

    The Stratix V version instead gives you the credit limit. This is the value stated in the specification (see the Flow Control Update Loop chart in the Altera PCIE IP manual). There are two values, the consumed and the limit. For the consumed you just count the credits you send (each header is one header credit, each 16 bytes of data is one data credit). The limit is what the root lets you have. Then do like the read/write pointers of a FIFO, simply subtract the consumed from the limit even if they wrap around, and you will have the available.