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Altera_Forum
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16 years ago

Problem with altpll output

I use EP2C8Q, the input clock connect the clk3 pin. the frequency is 27MHZ, I want to get higher frequency clock. I use the altpll to multiplier. The multiplication is 2 and 4. When I measure the out...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Connecting PLL outputs through dedicated "pll_outxx" pins reduces the jitter. It's recommended, when low jitter is a design objective. But it's not generally required. In some designs, e.g. DDR RAM controller, regular IO is preferred for clock outputs to achieve particular timing constraints.