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Altera_Forum
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14 years ago

Problem running pin_assignments.tcl script with uniPHY DDR3 controller

Hi,

I'm experiencing some problems with SoPC builder and quartus 11.0.

Why SoPC builder and not Qsys ? Because I use an IP that is'nt yet avaible with Qsys...

I did a very simple project with SoPC buider :

For a Stratix IV device :

- Nios II processor

- DDR3 controller with uniPHY

Building the system with SoPC builder is OK. Analysis & Synthesis are OK.

After that I did : Tools -> Tcl scripts, then I selected and launched <>_pin_assignments.tcl script.

Here is the log (tcl console) : 


 
ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object.
    while executing
"get_node_info -cell $node_id"
    (procedure "is_node_type_pll_clk" line 2)
    invoked from within
"is_node_type_pll_clk $pll_output_node_id"
    (procedure "get_input_clk_id" line 2)
    invoked from within
"get_input_clk_id $pll_ck_clock_id"
    (procedure "ddr3top_p0_get_ddr_pins" line 237)
    invoked from within
"ddr3top_p0_get_ddr_pins $instname allpins"
    (procedure "ddr3top_p0_initialize_ddr_db" line 13)
    invoked from within
"ddr3top_p0_initialize_ddr_db ddr_db"
    (file "D:/dev_fpga/test_ddr3_11/sopc/ddr3top/altera_mem_if_ddr3_phy/ddr3top_p0_pin_assignments.tcl" line 191)

If someone has an idea... Similar projects worked well with the same procedure with Quartus 10.1...

Thank you.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Here is an example of a Python script which can do all the job for you, just replace the path and the name of your top level entity generated sy SoPC builder : 

    
f = open('./src/sopc/your_sopc_top_level.vhd')
text = f.read()
f.close()
new_text = text.replace("mem_cas_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cas_n : OUT STD_LOGIC;")
new_text = new_text.replace("mem_ck : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ck : OUT STD_LOGIC;")
new_text = new_text.replace("mem_ck_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ck_n : OUT STD_LOGIC;")
new_text = new_text.replace("mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cke : OUT STD_LOGIC;")
new_text = new_text.replace("mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cs_n : OUT STD_LOGIC;")
new_text = new_text.replace("mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_odt : OUT STD_LOGIC;")
new_text = new_text.replace("mem_ras_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ras_n : OUT STD_LOGIC;")
new_text = new_text.replace("mem_we_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)", "mem_we_n : OUT STD_LOGIC")
new_text = new_text.replace("mem_cas_n(0)", "mem_cas_n")
new_text = new_text.replace("mem_ck(0)", "mem_ck")
new_text = new_text.replace("mem_ck_n(0)", "mem_ck_n")
new_text = new_text.replace("mem_cke(0)", "mem_cke")
new_text = new_text.replace("mem_cs_n(0)", "mem_cs_n")
new_text = new_text.replace("mem_odt(0)", "mem_odt")
new_text = new_text.replace("mem_ras_n(0)", "mem_ras_n")
new_text = new_text.replace("mem_we_n(0)", "mem_we_n")
f = open('./src/sopc/your_sopc_top_level.vhd', 'w')
f.write(new_text)
f.close()