Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThank You, It works.
- Replace, std_logic_vector (0 downto 0) by std_logic for : mem_cas_n mem_ck mem_ck_n mem_cke mem_cs_n mem_odt mem_ras_n mem_we_n - Replace, for all the above signals, mem_(0) by mem_x