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Altera_Forum
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15 years ago

Problem running pin_assignments.tcl script with uniPHY DDR3 controller

Hi, I'm experiencing some problems with SoPC builder and quartus 11.0. Why SoPC builder and not Qsys ? Because I use an IP that is'nt yet avaible with Qsys... I did a very simple p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Aha - I think I have found it. It is basically the same problem as described in solution rd05232011_576. (Search for this on the Altera website). I would post a link but the forum won't let me :-(.

It is not EXACTLY the same problem, but I have changed the std_logic_vector(0 downto 0) to std_logic in the component definition for the verilog sub-entity, and changed the mappings to the form:

mem_ck => mem_ck(0).

I hope this helps