Honored ContributorHi:
I use Altgxb IPcore to design a transceiver with EP4SGX230KF40 in quartus II 9.1. When i do timing simulation in modelsim 6.5b,the busy signal in reconfig module could set to '1' in several ns but never went to '0'. What should i do? Thanks
Honored ContributorI haven't simulated the reconfig module for Stratix IV GX yet. However, I seem to remember a few issues with Stratix II GX:
http://www.altera.com/support/kdb/solutions/rd06292006_250.html?gsa_pos=1&wt.oss_r=1&wt.oss=alt2gxb_reconfig%20simulation And I'm trying to find it but it seems you had to manually force a signal low at the beginning of the simulation. JakeHonored ContributorApparently, your reset circuitry does not initialize the GX properly. The busy signal not deasserting means the transmitter part is not ready for data traffic, let alone the receiver part. Are you (de)asserting the pllpowerdown, tx_digitalreset, rx_analogreset and rx_digitalreset signals in the right manner?
Can you post the code of your reset sequence state machine? You should read page 4-4 onwards, (chapter 4 of handbook vol.2). Especially figure 4-4 on page 4-8 contains a lot of essential info.
