problem of LCD controller

The Verilog always block can't be translated line by line, the syntax for a synchronous process with asynchronous reset is somewhat different. In my opinion, it's more intuitive than the respective Verilog construct that uses the negedge keyword for a level sensitive condition. You can use the language templates in Quartus editor context menu to look up the correct VHDL syntax for common design constructs.

process(iCLK,iRST_N)
variable var_mDLY : std_logic_vector(17 downto 0);
begin
if iRST_N='0'  then 
  LUT_INDEX <=(others =>'0');
  mLCD_ST <=(others =>'0');
  mDLY <=(others =>'0');
  mLCD_Start <='0';
  mLCD_DATA <=(others =>'0');
  mLCD_RS <='0';
elsif iCLK 'event and iCLK='1' then -- you can also write rising_edge(iCLK) 
end if;
end process;