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Altera_Forum
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16 years ago

Problem in read cycle with ddr2 controller

Hello, i am developing a board using Cyclone 2 and interface with DDR2 MT47H64M16HR-3 using DDR2 Megacore in SOPC (not High performance one), with CL = 5, WL = 4. It seems that there is no problem...
Altera_Forum's avatar
Altera_Forum
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15 years ago

There is no problem! First DQS toggling is known as Preamble and it is a requirement