Problem in ALTASMI IP quartus ver 12.1 with ECPS device

The observed behaviour, sampling of serial flash data output at falling DCLK edge has been preserved in the recent ALTASMI IP. But apparently it doesn't usually cause problems. According to the datasheet specification, all EPCS respectively M25Pxx devices have 0 ns minimal output hold time. But you still have sufficient FPGA DCLK output and DATA0 input delay to read valid data.

There may be problem because the clock output is directly connected to ALTASMI clkin. So in special cases, the ALTASMI registers might undergo a larger routing delay than DCLK, eating up the positive slack created by the IO delay. Timing constraints can avoid this situation.

But I agree that the serial flash interface is slow enough to switch from late to center MISO sampling, as apparently achieved in the suggested mod by michanisani.

The other point, unwanted continuous DCLK demands for code modification anyway. A possible fix is gating logic for DCLK, as in the below VHDL snippet. It's designed in a way that not glitches during nCS activation occur. As a side effect, DCLK will be delayed so that the need for changing the sampling edge has been probably obsoleted.

clkin_gated <= clkin_wire OR (scein_wire AND scein_delayed);
process (clkin_wire, reset)
  begin
    if reset = '1' then
      scein_delayed <= '1';
    elsif rising_edge(clkin_wire) then
      scein_delayed <= scein_wire;
    end if;
  end process;
cycloneii_asmiblock2 :  cycloneii_asmiblock
PORT MAP ( 
  data0out => wire_cycloneii_asmiblock2_data0out,
  dclkin => clkin_gated, --originally clkin_wire,
  oe => oe_wire,
  scein => scein_wire,
  sdoin => wire_cycloneii_asmiblock2_sdoin
);

If you don't want to edit the ALTASMI code, you can also connect the EPCS pins explicitely and put the gating logic between ALTASMI and the external pins.