Forum Discussion
Problem detecting PHY
Hi all,
I am coding my ethernet manually without RTOS or Nichestack on the DE4. My first step was to reset the MAC. - That can be done successfully The second step was to init the MAC.
alt_u8 i;
alt_u16 phyid1, phyid2;
/* perform scanning and get phy hardware */
for (i =0; i < 0x20; i++)
{
IOWR_ALTERA_TSEMAC_MDIO_ADDR0(TSE_MAC_BASE, i);
/* read phy address */
phyid1 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE, 0, 2);
phyid2 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE, 0, 3);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 15);
if (phyid1 != phyid2){
printf ("phy found:id1 %x, id2 %x\n", phyid1, phyid2);
break;
}
}
I am unable to find the PHY. Any pointers ? Cheers11 Replies
- Altera_Forum
Honored Contributor
Why not to use a driver, already supplied in examples?
- Altera_Forum
Honored Contributor
For my project, there are some licensing issues so I am trying to workaround them.
Also, I faced problems getting the demo to work on my board so to cut things short I studied some code from a friend that has successfully done this. Unfortunately this colleague has left the company so I am left with chunks of his code to reverse. Hence hitting this wall. So any help would be greatly appreciated. - Altera_Forum
Honored Contributor
Do you have a license for the Ethernet IP core? IF not, be sure not to close the opencores evaluation window. If you do then the TSE core will stop working and won't communicate on the MDIO lines.
You can also use signaltap probes to see if anything is happening on those lines. - Altera_Forum
Honored Contributor
--- Quote Start --- Do you have a license for the Ethernet IP core? IF not, be sure not to close the opencores evaluation window. If you do then the TSE core will stop working and won't communicate on the MDIO lines. You can also use signaltap probes to see if anything is happening on those lines. --- Quote End --- Well, this is strange. Say, I have no window at all because I ran from command line. Then, when I hit Ctrl+C or kill the programmer with "kill -9", the TSE core still works. For like an hour. - Altera_Forum
Honored Contributor
I don't know how the evaluation works from the command line. But I know that if the JTAG communication is interrupted, then the core works for a limited amount of time, usually 1-2 hours. It's probably the same when killing the programmer application.
- Altera_Forum
Honored Contributor
I am running an evaluation license whereby I leave the board thethered to my pc so I think it is still running.
I think the bigger problem would be that I am unable to communicate with the PHY through the MDIO - Altera_Forum
Honored Contributor
Well, at least a driver supplied with LwIP example works for me. It even works fine with my custom PHY initialization structure: I use KSZ9021 1Gbit PHY from Micrel, which is not supported by default.
- Altera_Forum
Honored Contributor
You should check the MDIO signals with signaltap, and see if the PHY is trying to answer something on any of the 32 addresses
- Altera_Forum
Honored Contributor
And also check if You use MDIO tristate correctly.
- Altera_Forum
Honored Contributor
I have never set up signaltap but will check the state of the pins.
I used the system builder to setup the pins on the board so no idea. Thanks. p.s. Socrates, is there a guide on how to use LWIP with the TSE without an RTOS? or some kind of example? I'm a bit of a newbie so need as much help as I can. Thanks