problem about altlvds PIN assignment!

Go to www.altera.com and go to Support-> My Support. You can file a Service Request there. That's how to get an engineer to look at the issue, where this is just a board for people to help each other and bounce ideas around.

And no, a timing sim is not static timing analysis. Static timing analysis is a bound analysis of all your delays in relation to your clocks. For example, if you have a 100Mhz clock, then your data delay can be anywhere between 0-10ns and the transfers will occur all right(I'm ignoring clock skew, but static timing analysis does a full-analysis of clock skew).

Timing sims are just a single number. For example, most timing sims are with the slow model, so let's say your data path was modeled as 12ns. You would not get an error in the sim, unless your testbench actually failed because the data transfer occurred one cycle later. The only time timing sims give errors is if they violate the micro-setup/hold of the destination register, which means the data has to change within a ~50ps window around the clock.

A good example would be across a bus. Let's say the entire bus delay was 12ns, and your testbench won't fail because it still sees all the data come over together. But in hardware they're going to be worst case 12ns, but might be a lot faster. So let's say some paths are 9ns. If your clock edge occurs at time 10ns, then these shorter paths have already transferred their data while the longer paths have not. Your timing sim would not catch this, but static timing analysis would.