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Altera_Forum's avatar
Altera_Forum
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16 years ago

problem about altlvds PIN assignment!

I want to use the altlvds megafunction to receive 500Mbps data(width=1),and the deserialization factor is 2.But now I face a strange problem: if i use verilog to implement the function and assig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

By timing issue I meant with another place and route, the delays to outputs will vary and your outputs might not line up anymore. That's not the issue if you're seeing all 0s though. You may want to submit an SR to get someone to look at it. Is the PLL locking?

Also might want to search the forums for discussions about doing timing sims. I find very few designers do these nowadays, as they tend to waste time and not find any issues that can't be uncovered with RTL sims and static timing analysis. Of course you're looking for a reason rather than "don't do that", but thought it was worth mentioning.