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Altera_Forum
Honored Contributor
Honored Contributorprevent write/write collision in on-chip True Dual Port Ram
Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_ForumHonored Contributor
Honored ContributorYou'll probably need some kind of mutual exclusion lock anyway - most likely if two fields must be updated together.
Commenting in the code which cpu writes to which variables (or structure members) will highlight any places where you might have a write-write collision. Separating things out completely will generate ugly unmaintainable code.
