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Altera_Forum
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11 years ago

prevent write/write collision in on-chip True Dual Port Ram

Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I think the collision prevention would be quite a logic burdon, hardly used and difficult when the two processors are on different clock domains. Unless some major customers asked for it, I cant see it making it into the core.