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Altera_Forum
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11 years ago

prevent write/write collision in on-chip True Dual Port Ram

Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks all for your inputs

I think the easiest way would be, to make an exclusive ram or address range for each CPU to write into it. However it would be nice if Altera implement such collision prevention in thier IP core.