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Altera_Forum
Honored Contributor
Honored Contributorprevent write/write collision in on-chip True Dual Port Ram
Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_ForumHonored Contributor
Honored ContributorNo - that Xilinx constraint is an additional one (I don't think and Altera memory has that constraint), the link to page 17 gives the equivalent to the altera constraint.
