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Honored Contributor
Honored Contributorprevent write/write collision in on-chip True Dual Port Ram
Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_ForumHonored Contributor
Honored ContributorXilinx embedded memories have the same problem, of course. However, it has an attribute RDADDR_COLLISION_HWCONFIG to mitigate the effect of a collision.
It's described on page 33 of this user guide: http://www.xilinx.com/support/documentation/user_guides/ug363.pdf
