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Altera_Forum
Honored Contributor
Honored Contributorprevent write/write collision in on-chip True Dual Port Ram
Hi, FPGA: Cyclone V SoC On-chip Memory: Ram, True Dual Port, single clock, Old_data Two NIOS will have access to the ram (NIOS A to Ram port S1, NIOS B to Ram port S2) In Altera docume...
Altera_ForumHonored Contributor
Honored ContributorYou cant really avoid it in HDL code. If both sides were using the same clock, you could give one side preference over the other, and disable the write enable for the other side. But on different clocks, the clock domain crossing would prevent that.
The easiest way would be to have just two memories. A -> B comunication and B -> A communication.
