prefetchable/non-prefetchable memory

32 vs. 64 bit is the address bus width, not the data bus width, you know? And depending on your PCI BAR size, you’ll just see a fraction of these 64 bits of PCI address internally.

I would be more concerned with the choice of prefetchable vs. non-prefetchable and the implication about data consistency and order of access. And the question how to bridge the gap to high-performance data transfers, i.e. DMA.

With DMA you typically have just one BAR for a small number of non-prefetchable registers. Reading such a register might have side effects and must be in-order, so a prefetchable memory BAR is a no-go for such a register.