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Altera_Forum
Honored Contributor
13 years agoWe have 4 BAR defined (0, 2, 3 and 4).
The last one uses the PCIe to Avalon master bridge and so can access a lot of Avalon slaves. (Don't ask why some of the others are separate!) You do have to be careful about how the PCIe slave window in mapped into Avalon address space, there are some strange assumptions made - it some cases it might be necessary to feed the Avalon master signals through a 'conduit' to generate the correct, fixed, upper address bits.