Point me in the right Direction - PCIe

Well, modern top/bottom-half driver architectures manage their interrupt load based on the current CPU/packet load. At a low packet rate or CPU load, each packet might issue a call to the interrupt handler (the top half) while at a higher packet rate, interrupt generation is only requested by the driver if all pending work was done. So, at a high load, the interrupt entry/exit overhead would vanish while your suggested spins would not only be more frequest at higher packet rate but also last longer if the system is loaded with I/O requests. And, of course, the spins eat precious CPU cycles that should be spent handling the high load.