PLL generates an incorrect 2x clock

Hi!

I'm using 2 PLLs on Arria 10 (10AX027H4F34I3SG) to create clocks. Both reference clocks are LVDS. The 3 clocks of one PLL are normal. In addition, the 2 clocks of the another PLL output become the set frequency doubling. The worng PLL reference clock is 64 MHz. It sets the output clock to 64MHz and 120MHz, but the actual output frequency is 128MHz and 240MHz.

Thanks in advance!