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SherwinKim's avatar
SherwinKim
Icon for New Contributor rankNew Contributor
4 years ago

PLL generates an incorrect 2x clock

Hi!

I'm using 2 PLLs on Arria 10 (10AX027H4F34I3SG) to create clocks. Both reference clocks are LVDS. The 3 clocks of one PLL are normal. In addition, the 2 clocks of the another PLL output become the set frequency doubling. The worng PLL reference clock is 64 MHz. It sets the output clock to 64MHz and 120MHz, but the actual output frequency is 128MHz and 240MHz.

Thanks in advance!

3 Replies

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    Is this observation related to simulation or on board measurement?


    Regards


  • SherwinKim's avatar
    SherwinKim
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi,

    It has been solved.

    The reason is that the pin has external termination and has not been set before.

    When the LVDS clock enters the FPGA, the P / N signal will be superimposed occasionally.