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SherwinKim
New Contributor
New ContributorPLL generates an incorrect 2x clock
Hi!
I'm using 2 PLLs on Arria 10 (10AX027H4F34I3SG) to create clocks. Both reference clocks are LVDS. The 3 clocks of one PLL are normal. In addition, the 2 clocks of the another PLL output become...
SherwinKimNew Contributor
New ContributorHi,
It has been solved.
The reason is that the pin has external termination and has not been set before.
When the LVDS clock enters the FPGA, the P / N signal will be superimposed occasionally.
