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Altera_Forum's avatar
Altera_Forum
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10 years ago

PLL does not lock anymore after connecting DDR3

Hi I'm designing a system with an NIOS and a DDR3 HMI. The fist shot was to implement the NIOS with internal RAM and a PLL. The PLL generates 50MHz from my connected 25MHz crystal. This s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Well the problem was that the RREF pin. After connecting it correctly it worked:

Cyclone® V Device Family Pin Connection Guidelines:

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.