Please, advise me how to improve the performance of my verilog module

Hi,

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Try changing the Optimization Technique from Balanced to Speed.

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I have several (not all) optimizations switched on for speed.

If I synthesizing one instance of this module in the complete project, I am getting FMax=330MHz. If I have 10 instances, then FMax=310MHz only :(

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Add two more register levels: register the inputs and the outputs.

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Please, help me with short example on it, I did not get the idea!

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How are you obtaining that 330MHz? Are you synthesizing your entire design or just that module?

Which is the critical path?

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Actually, I measure FMax for entire design, but it is not too complicated, right now the inputs are set from HSTC LVDS data, and the output is pipelined over "artificial part" to GPIO.

I am newbie in FPGA design, I just turned into this field after 20 years massively parallel numerical math experience. I tried to follow "set_false_path" but it seems that I did not set it properly and cannot understand how to figure out where is my critical part.

PS: I can publish entire project, it is just 600 lines, 100 lines already here, 300 lines just from Terasic, the rest one just binding different inputs and outputs to each other.

Sincerely,

Ilghiz