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Altera_Forum's avatar
Altera_Forum
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15 years ago

Please, advise me how to improve the performance of my verilog module

Hi, exercising on DE3 Terasic board, I meet a situation that I cannot find myself a solution of my questions and kindly ask this forum to advise me. I have small verilog module that reads ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Dumb suggestion one:

Try changing the Optimization Technique from Balanced to Speed.

Dumb suggestion two:

Add two more register levels: register the inputs and the outputs.

How are you obtaining that 330MHz? Are you synthesizing your entire design or just that module?

Which is the critical path?