Please, advise me how to improve the performance of my verilog module

I see, I misinterpreted the doc. :)

Anyway, taking a second look at your code, if I reading this right, it can't be mapped to the 4-M-A mode.

The 4-M-Adder performs the operation "output = (a0*b0) + (a1*b1) + (a2*b2) + (a3*b3)" with 3 levels of registers (for fMAX)

ra0 <= a0; ... rb3 <= b3;

rma01 <= (ra0 * rb0) + (ra1 * rb1)

rma23 <= (ra2 * rb2) + (ra3 * rb3)

rma <= rma01 + rm23;

output <= round_saturate(rma);

Or you can use it in 4-M-Accumulator mode

ra0 <= a0; ... rb3 <= b3;

rma01 <= (ra0 * rb0) + (ra1 * rb1)

rma23 <= (ra2 * rb2) + (ra3 * rb3)

rma <= rma01 + rm23 + rma;

output <= round_saturate(rma);

You need to, somehow, convert your algorithm into one of these patterns.

But looking at it, I can't figure out a way.