Please, advise me how to improve the performance of my verilog module

Hi,

thank you for your kind respond. May I try to comment your answer and probably figure out the main problem that forced me to ask at this forum.

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Quartus will infer the four multiplier adder mode from your Verilog, if it follows a suitable template.

Check the Quartus manual, section 6-9, for details and examples.

http://www.altera.com/literature/hb/...s_qii51007.pdf (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf)

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yes, it is one reason why I am asking at this forum.

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That said, I don't see how it will help your with your resource problem: a Stratix III DSP block can implement 4 18x18 multipliers, weather it's 4 independent multipliers or 4 multipler-adders.

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No! Actually at the Altera document

http://www.altera.com/literature/hb/stx3/stx3_siii51005.pdf

at page 5-2, there is a table 5-1 that says if for SL150 I use four multiplier mode I can achieve 384 18x18 multipliers, otherwise if they are just normal (independent) multipliers, I am achieving only 192 18x18 multipliers. I need more performance!!!

From the other hand, at

http://www.altera.com/literature/hb/stx3/stx3_siii5v2.pdf

at page 1-17 and table 1-21 at 5-th line I should achieve 600 MHz at 18x18 mode and 440 MHz at double mode (I have C2 speed grade). I need more speed (FMax) for my project!!!

Hence I am trying to find the solution how to organize my computation such a way to achieve this performance.

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PS: your "artificial block" looks like something that will be synthesized to latches.

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Please, do not care about it! In the reality it is completely different algorithm in this "artificial block" but it is about 2000 lines and these lines can take you our of my main question.

Sincerely,

Ilghiz