Please, advise me how to improve the performance of my verilog module

Hi,

Quartus will infer the four multipler adder mode from your Verilog, if it follows a suitable template.

Check the Quartus manual, section 6-9, for details and examples.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

That said, I don't see how it will help your with your resource problem: a Stratix III DSP block can implement 4 18x18 multipliers, weather it's 4 independent multipliers or 4 multipler-adders.

As for fMax, you need to take a look at your critical paths and see where the largest delay is. In such a case, adding some extra register stages might help.

PS: your "artificial block" looks like something that will be synthesized to latches.