Hi Sstrell,
That means I have to make the system from scratch, including adding IPs and all. I design a model in DSP Builder, I run it, and get a .qpf file generated by DSP Builder. I create a .qsys file for the .qpf file generated by DSP Builder example for FFT. And, I created a board XML file. Yes, I got the same GUI interface, only clk and resets. I think now I have to add IPs and all and make a connection between the IPs, and run it in an FPGA. By default, there are clk and resets. I can add the IP i designed from DSP Builder, generate files from this platform designer, and compile it in Quartus to get a bitstream. So fat this is my understanding.