pipeline bridge bursting and clock crossing bridge fifo length

One more question if you don't mind answering,

What is the exact burst length of DDR2 SDRAM Controller with ALTMEMPHY when using High Performance Controller II? In SOPC Builder after instantiating DDR2 SDRAM Controller with ALTMEMPHY, in the Controller Settings tab, I set "Local Maximum Burst Count" to 8, "Memory Burst Length" is also set to 8 beats under Memory Settings tab inside "Modify Parameters", and to match this my Avalon burst count signal to the DDR2 Controller is 3 bits wide.

There is still 1 burst adapter being instantiated by SOPC. Do you know why this is happening?

p.s. Altmemphy documentation and design tutorial seems to suggest that that burst length is 8 for High Performance Controller II, but the burst adapter still gets created...