pipeline bridge bursting and clock crossing bridge fifo length

So do you mean that for SDR SDRAM (is this the same as the one listed as "SDRAM Controller" in SDRAM section of SOPC builder?), you would get the same memory bandwidth if you burst for 10 read transfers, or if you do 10 read transfers one after another? Doesn't one SDRAM read take tens of cycles?

EDIT: I guess you are suggesting me to use pipelined transfers instead of bursts. What I experienced to be the problem with pipelined transfers is that, let's say I have two master components which will have DMA to SDRAM. Both will use pipelined transfers and both are equally important to have high bandwidth so I can't assign more arbitration shares to one over another. When both components post pipelined reads to SDRAM at the same time, Arbitration alternates between the two components (granting first read to component 1, then second read to component 2, then third read to component 1 again.. etc) , hence causes a VERY long latency to occur to both components. Is there a way to for Avalon masters to gain arbitration lock, without using bursts??

Thanks for your help!