pipeline bridge bursting and clock crossing bridge fifo length

A memory doesn't have to support bursting to be able to return data every clock cycle. Bursting is meant for interfaces that do not perform efficiently without back to back sequential data. The SDR SDRAM controller was designed to avoid the need to burst offchip; however, if you connect many masters up to it you might want to increase their arbitration shares to improve your memory efficiency. So if you are using the SDR SDRAM and on-chip RAM components there is no reason to enable bursting on any of your masters.