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Altera_Forum's avatar
Altera_Forum
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14 years ago

pipeline bridge bursting and clock crossing bridge fifo length

Hello, I'm new to Qsys/SOPC Builder and I'm currently developing a Nios II system and have problems to understand what the effects and the dependencies of the mentioned features are. The C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your reply.

I was talking about the SDRAM on the DE2 board and listed as SDRAM controller in SOPC (which I think is the same as the one you mentioned?)

When you say that onchip-RAM and SDRAM do not support bursting, do you mean that the readdata isn't returned in consecutive cycles after the initial delay (hence essentially same as requesting for data separately), or that burst adapters will be created in order to support bursts?

The reason I ask is because in simulation I do see that readdata IS being returned in consecutive cycles after the initial delay.

Thanks for your help!