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Altera_Forum's avatar
Altera_Forum
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14 years ago

pipeline bridge bursting and clock crossing bridge fifo length

Hello, I'm new to Qsys/SOPC Builder and I'm currently developing a Nios II system and have problems to understand what the effects and the dependencies of the mentioned features are. The C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

On-chip memory doesn't support bursting (don't make sense to burst into on-chip RAM). I assume you are talking about the old SDR SDRAM controller listed in SOPC Builder/Qsys? If so it doesn't support bursting either.