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Altera_Forum's avatar
Altera_Forum
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14 years ago

pipeline bridge bursting and clock crossing bridge fifo length

Hello, I'm new to Qsys/SOPC Builder and I'm currently developing a Nios II system and have problems to understand what the effects and the dependencies of the mentioned features are. The C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

how do you find out what the max burst size is for components? For DDR2 high performance controller there is an option to choose max burst size, but for onchip-RAM or SDRAM controller, what is the maximum burst size? I'm trying to get rid of all burst adapters since they are on my critical path.

Thanks for your help!