pipeline bridge bursting and clock crossing bridge fifo length

That's correct. If you had say a burst of 8 master accessing a slave that only handles a max burst of 2, a burst adapter will be created in the fabric for you. The adapter will chop the burst into four individual bursts of 2. All of this is transparent to the master and slave.

I would recommend just placing main memory, Nios II, and Ethernet on the fast domain then all your slow peripherals can be placed behind a clock crossing bridge. Then if you have timing failures then you can evaluate placing pipeline bridges into the data path of the faster clock domain.

I'm on a mobile device so it is a bit clumsy to link you to the doc. Go to the Nios II literature page and look for the embedded design handbook, one of the chapters talks about optimizations for MM.