pipeline bridge bursting and clock crossing bridge fifo length

Just to make sure I understood it correctly: If the burst count width of the master is greater than the burst count width of the slave the tool will generate logic so that the burst transfer is automatically split to smaller burst cycles which the slave can handle?

The system I'm working on is a NiosII processor system. It's based on the Ethernet example for the Embedded Systems Development Kit, Cyclone III Edition. Ideally the target clock frequency of the system would be 125 MHz for the processor. We plan to replace the DDR2 memory with SRAM. There are some peripherals connected which clock at 125 MHz and 62.4 MHz.

The first step for implmenting a system would be to import the needed modules into and add clock crossing bridges where needed. The synthesize the design and look for timing requirements which were not met and then add Pipeline Bridges where the timing requirements were not met?

Unfortunately I wasn't able to finde the document you mentioned. Can you tell me where I can find this document? I am working mostly with the following two documents right now:

Section II. System Design with Qsys of the Quartus II handbook and

Avalon Interface Specifications