pipeline bridge bursting and clock crossing bridge fifo length

Larger FIFO depth will increase the on-chip memory utilization. If you increase the FIFO in small steps you might find the same number of RAM blocks are used. When you increase the command queue the read queue must be increased too since it'll need more support more posted reads in flight. Picking those depths is tricky since it's system depended, without knowing what you are doing I can't comment on it.

When you have a burst mismatch between the master and slave the tools will adapt it. For big to small burst it'll chop the burst up. For small to big it'll pad the upper burst bits to 0 so that the burst width matches the end point.

Try designing without pipeline bridges then add them when needed. I use pipeline bridges when I have the following ratios to pipeline the fabric logic to meet timing:

many masters connected to a slave

master connected to many slaves

I recommend reading the document titled something like "Avalon optimization guide". Those ratios are covered in more detail about what features to enable. Note there is another guide that is Qsys specific so make sure you grab the right one for whatever tool you are using. If you are getting started on a project you might want to try out Qsys.